- Bnc-faculty-all-list - ecn.purdue.edu

FW: BNC Faculty Seminar Series
by Abrol, Sangeeta Saddul 18 Nov '21

18 Nov '21

Here is a Reminder of the Faculty Seminar Series for today. Thanks, Sangeeta Hi All - This week Speaker for the Faculty Seminar Series is Brett Savoie, Charles Davidson Assistant Professor of Chemical Engineering and the topic is "How Things Fall Apart: Learning from Degradation Chemistry". Best, Sangeeta Sangeeta Abrol Via Jaime Turner is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://purdue-edu.zoom.us/j/98695180597 Meeting ID: 986 9518 0597 One tap mobile +16465588656,,98695180597# US (New York) 13017158592,,98695180597# US +(Washington DC) Dial by your location +1 646 558 8656 US (New York) +1 301 715 8592 US (Washington DC) +1 312 626 6799 US (Chicago) +1 669 900 6833 US (San Jose) +1 253 215 8782 US (Tacoma) +1 346 248 7799 US (Houston) Meeting ID: 986 9518 0597 Find your local number: https://purdue-edu.zoom.us/u/abtkh4zmcl

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BNC Faculty Seminar Series: Brett Savoie, Charles Davidson Assistant Professor of Chemical Engineering
by Abrol, Sangeeta Saddul 15 Nov '21

15 Nov '21

Hi All - This week Speaker for the Faculty Seminar Series is Brett Savoie, Charles Davidson Assistant Professor of Chemical Engineering and the topic is "How Things Fall Apart: Learning from Degradation Chemistry". Best, Sangeeta Sangeeta Abrol Via Jaime Turner is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://purdue-edu.zoom.us/j/98695180597 Meeting ID: 986 9518 0597 One tap mobile +16465588656,,98695180597# US (New York) 13017158592,,98695180597# US +(Washington DC) Dial by your location +1 646 558 8656 US (New York) +1 301 715 8592 US (Washington DC) +1 312 626 6799 US (Chicago) +1 669 900 6833 US (San Jose) +1 253 215 8782 US (Tacoma) +1 346 248 7799 US (Houston) Meeting ID: 986 9518 0597 Find your local number: https://purdue-edu.zoom.us/u/abtkh4zmcl

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FW: nanoHUB Hands-on Machine Learning Workshop
by Black, Nancy Lee 15 Nov '21

15 Nov '21

nanoHUB is excited to announce that a new workshop has been scheduled in the Fall 2021 session of our Hands-on Data Science and Machine Learning Training Series. Series information: Our series is aimed at active researchers and educators and designed to introduce practical skills with online, hands-on activities that participants will be able to incorporate in their own work. Hands-on activities will use nanoHUB cloud computing resources, negating the need to download or install any software. All that is required of the audience is an internet connection and an hour to spare for the demonstration. After the training sessions, you will be able to continue using nanoHUB for research or education. Recordings and associated materials from prior workshops can be found at the workshop webpage: https://nanohub.org/groups/ml/handsontraining<https://click.mail.nanohub.org/?qs=fa5d19fdba110be3328ac7c0e6aa1c23ed02fcba…> Register soon as seats are limited. Date/Time: Wednesday, November 17, 2021 / 1:00 PM - 2:00 PM EST Title: Integrating Machine Learning with a Genetic Algorithm for Materials Exploration Presenter: Joe D. Kern, Georgia Institute of Technology, Ramprasad Group Register for this workshop here<https://click.mail.nanohub.org/?qs=fa5d19fdba110be31df082c3e47a7f7022739f4c…> Abstract: The genetic algorithm is a computer algorithm inspired by nature: selecting parents of a generation via some fitness function, crossing-over the parent genes (reproduction), and randomly mutating the genes of the children. In this talk, we will explore how this algorithm can be used for materials discovery by: 1. Generating swift material property prediction using machine learning (ML) 2. Creating an algorithm to design new materials from combinations of prior ones 3. Integrating the ML property predictors with the design algorithm to discover new materials PolyGA, an implementation of the genetic algorithm for the polymer domain, will be used as the basis for this exploration. Bio: Joe D Kern is a Materials Science and Engineering graduate student at the Georgia Institute of Technology in the Ramprasad Group. Prior to graduate school, he dual majored in Materials Science and Computer Science at the University of Wisconsin - Madison and spent six years in the Minnesota National Guard as an Arabic Linguist. His research involves utilizing computational techniques, such as genetic algorithms and machine learning, to expedite materials discovery in the polymer chemical space. Regards, Alejandro Strachan Deputy Director, nanoHUB Arun Mannodi Kanakkithodi (he/him/his) Assistant Professor, School of Materials Engineering, Purdue University https://www.mannodigroup.com/

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Faculty Reviewers Needed for Next Week
by Abrol, Sangeeta Saddul 10 Nov '21

10 Nov '21

Volunteer faculty reviewers working in semiconductor/microelectronics are needed to help review applicants for the GEM Fellowship program, a national fellowship program serving underrepresented minority students. Purdue Engineering is a partner with the GEM consortium and we currently have 30 full or associate GEM fellows across the college. Review takes place November 17th - 19th in Alexandria, VA. A virtual option is available, or the College will cover the cost for a faculty reviewer to attend. There will be some networking opportunities with semiconductor companies such as Applied Materials, who will be seeking GEM fellows to work with them through the review process. Additional details are below. If interested, please contact as soon as possible: Janet Beagle, Sr. Director of Graduate Programs for Purdue's College of Engineering (jbeagle(a)purdue.edu<mailto:jbeagle@purdue.edu> or 49-40600). More information about the GEM Fellowship is available on their website https://gemfellowship.org/, and Janet is happy to answer any questions. The anticipated schedule is as follows (ALL TIMES ARE EASTERN TIME): * Welcome Event Date / Time: Wednesday, November 17, 2021 @ 6PM ET * Panel Review (Individual/Team): Thursday, November 18, 2021 @ 8:45AM - 3:00PM ET * Panel Review (Team): Friday, November 19, 2021 @ 8:45AM - 2:30PM ET Latest Participation in the GEM Fellowship Application Review Panel is a volunteer effort for those who are passionate about the GEM mission. GEM strongly encourages member employers and universities to nominate a review panelists, faculty or STEM graduate degree holding employees or researchers in industry, whom you would like to expose to the number of high performing, under-represented domestic candidates in STEM, available for recruitment, to participate. Please note the following for nominees/panelists: 1. Panelists must hold a PhD (preferred) or Master's in a science or engineering field to be confirmed as a panelist, and be a decision maker on supporting talent (desired). 2. Confirmed panelists must travel to Alexandria, VA in order to participate in the review panel, AND have full financial support (transportation, hotel and non-provided meals) to attend this meeting. (A virtual option is also available, or Purdue's College of Engineering will cover the travel for our volunteer.) 3. Confirmed panelists are VOLUNTEERS. There is no stipend or payment provided to confirmed panelists. 4. Panelists will be required to review approximately 40 applications at the panel meeting and to provide an individual rubric score. At the on-site panel meeting, panelists are paired in teams to determine the final composite score for each eligible applicant. GEM will provide a small thank you gift for participation. Thank you, Janet -------------------------------------------------- Janet Beagle, Ph.D. Senior Director of Graduate Programs Purdue University│College of Engineering Email: jbeagle(a)purdue.edu<mailto:jbeagle@purdue.edu> Phone: 765-494-0600

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FW: BNC E-news: Week of November 8th, 2021
by Abrol, Sangeeta Saddul 08 Nov '21

08 Nov '21

[cid:image006.png@01D7401C.A3F567B0] Seminars /Workshops / Events BNC Faculty Seminar Series (For Faculty Only) Dr. Caitlin Proctor Assistant Professor of Agricultural and Biological Engineering & Environmental and Ecological Engineering (by courtesy) at Purdue University Thursday November 11th, 2021 12:00pm – 1:00pm, Zoom Topic : Biofilms in Everyday Life Workshop Announcement LakeShore Cryotronics and Neil Dilley are hosting a workshop to highlight some new equipment in the Birck Spintronics Lab and present results from beta phase testing. These include: * LakeShore Synchronous Source-Measure system M81: sensitive, flexible, automated AC+DC electrical measurements system for, e.g., Hall effect (with gating), differential conductance, ESD-sensitive materials, and more. * LakeShore FastHall M91: DC resistance system with automated permutation of wiring for Hall effect and resistance measurements to quickly determine Hall coefficient, carrier concentration, carrier type and mobility. Both of these equipment are installed on the PPMS DynaCool cryostat in the Birck Spin Lab which provides an environment with T = 1.8 - 400 K and fields up to 9 tesla. We will also review other magnetic characterization capabilities and give lab tours during the lunch hour. November 10, 2021 10 AM - 3 PM In person @ BRK Rm 2001 Virtual: MS Teams link will be sent to registered attendees Please register here: https://tinyurl.com/vywnbte9 Thanks, Neil R. Dilley, Ph.D. Research Scientist Birck Nanotechnology Center , Rm 1010 1205 West State St. West Lafayette, IN 47907-2057 765-496-6080 Distinguished Seminar Series: Purdue Mechanical Engineering The Viskanta Fellowship Lecture Dr. Alan McGaughey Trustee Professor of Mechanical Engineering Carnegie Mellon University Wednesday, November 10, 2021 3:00 PM – ME1012 Topic: Integrating Theory, Simulation, Machine Learning, and Experiments to Solve Heat Transfer Problems Seminar for Neurotrauma and Diseases<https://vet.purdue.edu/cpr/Seminar%20for%20Neurotrauma.php> Sponsored by Plexon Neurotechnology Systems Wednesdays | 4-5pm | via Zoom 2021 Birck Nanotechnology Center Research Image Contest Sponsored by NSAC and Birck leadership - $600 in prize awards for student entries Please share your research images which showcase the beauty you’ve observed around you at Birck! All members of the Birck community – students, staff, and faculty – are welcome to submit their images that can include not only research images but also photos of life here at Birck. For research images, we ask that you also write a short paragraph explaining what we are looking at and why it is significant to you. We will assemble a panel of judges and announce awards at the BNC Holiday Party in December, and student entries are eligible to win: $300 for 1st place $200 for 2nd place $100 for 3rd place You can submit multiple images anytime between now and November 30, 2021 to a new MS Teams channel we have set up for the image contest, see link below: https://teams.microsoft.com/l/channel/19%3abf8be291dbb9468b831b6e0de523b930… If you have issues or questions, please email Neil Dilley at ndilley(a)purdue.edu<mailto:ndilley@purdue.edu> . Happy image hunting! [Text, logo, company name Description automatically generated] and the Birck Nanotechnology Center [A picture containing text, indoor, seat Description automatically generated][A picture containing background pattern Description automatically generated][A group of colorful feathers Description automatically generated with low confidence][A picture containing indoor, birthday, office, chocolate Description automatically generated][A picture containing tool Description automatically generated][cid:image015.png@01D7BEA6.8D0C2170][A close-up of a person's chest Description automatically generated with medium confidence] Birck Events<https://www.purdue.edu/discoverypark/birck/events/index.php> and Birck News<https://www.purdue.edu/discoverypark/birck/news/index.php> Thanksgiving Luncheon (BNC Staff only) [cid:image002.jpg@01D7D4AF.FB67FB20] JOB POSTINGS: R&D Senior Design Engineer at Alpha & Omega Semiconductor Alpha & Omega Semiconductor is looking for a Senior Design Engineer who will work in a dynamic team environment at AOS headquarter located in Sunnyvale, CA. The main responsibility of this position is to work with marketing/process integration/product engineering group to develop silicon power device technology. Application link: Senior Design Engineer - Sunnyvale, CA - Alpha & Omega Semiconductor Jobs (applicantpro.com)<https://caosmd.applicantpro.com/jobs/2050960.html> R&D Senior Process Integration Engineer at Alpha & Omega Semiconductor Alpha & Omega Semiconductor is looking for a Senior Process Integration Engineer who will work in a dynamic team environment at AOS Semiconductor's leading technology fabrication facility (Jireh Semiconductor) located in Hillsboro, Oregon. The focus of this position is to work with device/process module/product engineering group to develop silicon power device process technology and improve existing technology yield. Primary responsibilities are to process flow implementation, electrical characterization (failure analysis), and wafer level testing yield monitoring. Application link: Entry Level MS or PHD Process Integration R&D Engineer - Hillsboro, OR - Jireh Semiconductor Jobs (applicantpro.com)<https://aosmd.applicantpro.com/jobs/1949301.html> Opening in OxideMEMS lab Sunil Bhave’s OxideMEMS Lab <https://engineering.purdue.edu/oxidemems/publications.html> explores inter-domain coupling in Opto-mechanical, Spin-Acoustic and Atom-MEMS devices. PhD, Postdoctoral and Research Associate positions are available in these areas: · Superconducting qubit and cryo-CMOS circuits · Resonators and switches · MEMS-engine for LIDAR · Piezo-on-nitride transducers for atom-mechanics Expertise in many and most of Microfabrication, PiezoMEMS, Photonics, Quantum Mechanics, Microwave circuits, PCB design, ADS/HFSS, Comsol, Python and Labview is required. Please send CV to bhave(a)purdue.edu<mailto:bhave@purdue.edu> if you are interested.link<http://interested.link> [cid:image020.png@01D7BEAF.D3C3AE90] Postdoctoral Position – Nonlinear Nanophotonics – Deadline Nov.15, 2021 Fliers with more information posted on the bulletin boards. An electronics engineer position is available in the Smart Sensing and Electronics Systems Branch of NASA, located at the Glenn Research Center (GRC). The focus of the successful candidate will be on research, design, development, simulation and testing of sensing devices, transducers, components, and related circuitry for application to aerospace research and development endeavors. See https://www.usajobs.gov/GetJob/ViewDetails/615488500 for details. Contact Dallas Morisette morisett(a)purdue.edu<mailto:morisett@purdue.edu> for more detail Nanofabrication Engineer at Microsoft Microsoft Azure Quantum at Station Q Purdue seeks a nanofabrication engineer in the device fabrication group. You will join a multi-disciplinary team of theoretical and experimental physicists, materials scientists, and hardware and software engineers working at the forefront of quantum computing. You should have experience in device fabrication and characterization techniques. Our work at Station Q Purdue in West Lafayette, Indiana is part of global Microsoft Quantum research effort in topological quantum computing. Responsibilities: Responsibilities include develop, operate, and characterize semiconductor device fabrication processes in the Birck Nanotechnology Center cleanroom facilities located at Purdue University. Accurately documenting and effectively communicating all procedures and results to the larger research group is an essential aspect of the position. The candidate may also be required to assist in the maintenance of equipment. Qualifications: A successful candidate must have: • • Master’s degree in Physics, Materials Science or Electrical Engineering. Other engineering disciplines will also be considered. • • Hands-on experience working with some or all of the following semiconductor process areas: lithography, thin film deposition and etch. • • Ability to follow protocols to operate sophisticated experimental equipment and to safely work with industrial solvents, acids, and bases in a cleanroom environment • • Excellent written and oral communication skills. • • Proficiency at accurately documenting processes and protocols. • • Strong attention to detail and good organizational skills. • • Strong desire to work in a collaborative international team. Preference may be given to candidates with the following additional qualifications: • • Industry experience in semiconductor device process integration. • • Expertise in thin film characterization, both structural and electrical. • • Familiarity with design and layout tools for chip scale devices. Please send your resume to flgriggi(a)microsoft.com<mailto:flgriggi@microsoft.com>, selected candidates will be contacted for interviews. NSAC Fab Forum There will be no NSAC Fab Forum this Tuesday NSAC Coffee Hour There will be no NSAC Coffee Hour this Friday Birck Nanotechnology Center Advanced Capabilities Helios G4 UX Dualbeam SEM/FIB [Helios 5 UC DualBeam for Materials Science]Features: * Phoenix ion column with accelerating voltage range from 500V – 30kV and current range from 0.1pA-65nA * Electron beam resolution of 0.6 nm at 30kV * STEM detector with 0.7nm resolution at 1kV * EDX detector * Great for cross section imaging and chemical characterization, patterning, TEM sample prep, and 3D reconstruction Contact: Rosa E Diaz– rdiazri(a)purdue.edu<mailto:rdiazri@purdue.edu> (Staff in Charge), BRK 1237 ***To post an announcement in the weekly BNC E-news please send to Sangeeta Abrol @ abrols(a)purdue.edu***<mailto:abrols@purdue.edu***> Follow us on Facebook and Twitter [Facebook icon]<https://www.facebook.com/nano.purdue.edu/> [Twitter icon] <https://twitter.com/BNCPurdue>

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Webinar by Prof. Hadiseh Alaeian (Purdue) on "From Dipolar to Rydberg Photonics: Harnessing Atom-Atom Interactions"
by Gupta, Sumeet Kumar 08 Nov '21

08 Nov '21

Hello It is my pleasure to announce a webinar by Prof. Hadiseh Alaeian (Purdue University) in the ECE webinar series. The details are below and attached. Hope to see you in the webinar. Thanks Sumeet Gupta [cid:e00d4c63-3f26-44f2-b083-003db71270ea]

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BNC Faculty Seminar Series: Dr. Caitlin Proctor (This Seminar Faculty ONLY this week)
by Abrol, Sangeeta Saddul 05 Nov '21

05 Nov '21

THIS IS FOR FACULTY ONLY Sangeeta Abrol Via Jaime Turner is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://purdue-edu.zoom.us/j/98695180597 Meeting ID: 986 9518 0597 One tap mobile +16465588656,,98695180597# US (New York) 13017158592,,98695180597# US +(Washington DC) Dial by your location +1 646 558 8656 US (New York) +1 301 715 8592 US (Washington DC) +1 312 626 6799 US (Chicago) +1 669 900 6833 US (San Jose) +1 253 215 8782 US (Tacoma) +1 346 248 7799 US (Houston) Meeting ID: 986 9518 0597 Find your local number: https://purdue-edu.zoom.us/u/abtkh4zmcl

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Workshop : New Electrical Characterization Capabilities
by Abrol, Sangeeta Saddul 04 Nov '21

04 Nov '21

Hi All - -- Workshop: new electrical characterization capabilities at the Birck Nanotechnology Center November 10, 2021 10 AM - 3 PM In person @ BRK Rm 2001 Virtual: MS Teams link will be sent to registered attendees Please register here: https://tinyurl.com/vywnbte9 -- Thanks, Neil R. Dilley, Ph.D. Research Scientist Birck Nanotechnology Center , Rm 1010 1205 West State St. West Lafayette, IN 47907-2057 765-496-6080

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REMINDER: BNC Faculty Seminar Series Today: Tian Li, Assistant Professor of Mechanical Engineering
by Abrol, Sangeeta Saddul 04 Nov '21

04 Nov '21

Hi All - Here is a reminder and Bio/Abstract for this week's Birck Faculty Seminar Speaker : Tian Li, Assistant Professor of Mechanical Engineering. Thanks, Sangeeta Hi All- Sangeeta Abrol via Jaime Turner is inviting you to a scheduled Zoom meeting on Thursday November 4th at 12.00pm. Regards, Sangeeta Join Zoom Meeting https://purdue-edu.zoom.us/j/98695180597 Meeting ID: 986 9518 0597 One tap mobile +16465588656,,98695180597# US (New York) 13017158592,,98695180597# US +(Washington DC) Dial by your location +1 646 558 8656 US (New York) +1 301 715 8592 US (Washington DC) +1 312 626 6799 US (Chicago) +1 669 900 6833 US (San Jose) +1 253 215 8782 US (Tacoma) +1 346 248 7799 US (Houston) Meeting ID: 986 9518 0597 Find your local number: https://purdue-edu.zoom.us/u/abtkh4zmcl

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Update to Tomorrow's Day-of Agenda - PEDLS Lecture and Panel Session for Ravi Mahajan
by Abrol, Sangeeta Saddul 03 Nov '21

03 Nov '21

Dear all, I have a few updates to tomorrow’s PEDLS lecture and panel session day-of agenda. Please let me know if you have any questios or comments. For technical support, I can be reached directly on my cell, at 795-430-7176. Correction! In-person event so no registration is required. Thursday, November 4, 2021, at 2:30-4:45 PM (EDT) | MSEE Atrium LECTURE | 2:30-3:30 PM (EDT) | Title: The Coming “Not So Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry 2:00-2:20 PM (EDT) | Speaker and participants are encouraged to arrive in advance to prepare and test equipment. 2:30-2:35 PM (EDT) | Welcome, PEDLS Overview and Introduction of Dean Mung Chiang: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering Introduction of Ravi Mahajan: × Mung Chiang, Executive Vice President of Purdue University for strategic initiatives, John A. Edwardson Dean of the College of Engineering, Roscoe H. George Distinguished Professor of Electrical and Computer Engineering 2:35-3:15 PM (EDT) | “The Coming “Not-So-Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry” – Lecture presented by: Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation 3:15-3:30 PM (EDT) | Q&A and Conclusion: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering INTERMISSION | 3:30-3:45 PM (EDT) | Participants are encouraged to arrive in advance to prepare and test equipment. PANEL| 3:45-4:45 PM (EDT)| Title: The Future of MicroChips Design 3:45-3:50 PM (EDT) | Welcome and Introduction of Carol Handwerker (Moderator) by: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering Introduction of Panelists by Carol Handwerker (Panel Moderator): Moderator: * Carol Handwerker, Reinhardt Schuhmann Jr. Professor of Materials Engineering Panelists: * Zhihong Chen, Professor of Electrical and Computer Engineering * Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation * Anand Raghunathan, Professor of Electrical and Computer Engineering * Ganesh Subbarayan, Professor of Mechanical Engineering 3:50-4:30 PM PM (EDT) | “The Future of Microchips Design?” 4:30-4:45 PM (EDT) | Q&A and Conclusion: * Carol Handwerker, Reinhardt Schuhmann Jr. Professor of Materials Engineering Dean Mung Chiang’s Bio: Mung Chiang is the Executive Vice President of Purdue University for strategic initiatives, the John A. Edwardson Dean of the College of Engineering, and the Roscoe H. George Distinguished Professor of Electrical and Computer Engineering. Purdue Engineering in 2021 became the largest engineering school to ever ranked among top five in the U.S. During 2019-20, he served as the Science and Technology Adviser to the U.S. Secretary of State and the chief global technology office in the Department of State to launch Technology Diplomacy. Prior to 2017, he was the Arthur LeGrand Doty Professor of Electrical Engineering, the inaugural Chair of Princeton Entrepreneurship Council and Director of Keller Center for Engineering Education at Princeton University. His research on communication networks received the 2013 Alan T. Waterman Award, the highest honor to scientists and engineers under the age of 40 in the U.S. A recipient of a Guggenheim Fellowship and the IEEE Tomiyasu Technical Achievement Award, he was elected to the National Academy of Inventors and the Royal Swedish Academy of Engineering Sciences. He founded the Princeton EDGE Lab in 2009 and co-founded several startup companies and an industry consortium in mobile networks, IoT and AI. A recipient of the ASEE Terman Education Award, his textbooks and online courses have reached hundreds of thousands of students. PEDLS Overview & Introduction Statement: Beginning in 2018, the Purdue Engineering Distinguished Lecture Series invites world-renowned faculty and professionals to Purdue Engineering to encourage thought-provoking conversations and ideas with faculty and students regarding the grand challenges and opportunities in their fields. Besides presenting a lecture to a broad audience of faculty, graduate and undergraduate students, they engage in an interactive panel with Purdue faculty and students. * - Speaker: Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation Bio: Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award For Excellence and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. Link to bio.<https://eps.ieee.org/technology/9-about-cpmt/313-bio-mahajan.html> - Lecture Title: The Coming “Not So Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry Lecture Abstract: Advanced packaging technologies are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power efficient platforms. This talk will first review the evolution of packaging to set context and describe the increasing value of packaging as an HI platform. Different packaging architectures will be compared on the basis of their physical interconnect capabilities, power delivery, power removal, and high bandwidth signaling capabilities. Key features in leading edge 2D and 3D technologies, will be described and a roadmap for their evolution will be presented. Specific examples, showing how product implementations take advantage of these technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust advanced package architectures. In addition to performance characteristics, this talk will also illustrate key opportunities and challenges in materials development, manufacturability and reliability, and describe how well-defined industry-academia partnerships can continue to ensure successful evolution of the HI roadmap. Panel Title: The Future of Microchips Design Panel Abstract: Microelectronics system architecture design is at the cusp of a technological shift with pervasive application of intelligence, modular chiplet integration enabling hybrid multi-die architecture, with ensuing security concerns with untrusted chiplets including DoS, snooping and side channels. The corresponding package-level hardware trends include 2.5D system in package with silicon or organic interposers, thinned stacked dies, and photonic integration. Complementing these system architecture and packaging trends are beyond CMOS technologies and BEOL innovations including novel metal and dielectric materials, and integrating novel devices and technologies at the intermediate interconnect layers. This panel will explore the drivers behind the technological trends and the research priorities that must be addressed to enable the microchips of the future. Thank you, Maria • • • Maria Longoria-Littleton Assistant Director, Faculty Success Programs College of Engineering

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