Dear all, I have a few updates to tomorrow’s PEDLS lecture and panel session day-of agenda. Please let me know if you have any questios or comments. For technical support, I can be reached directly on my cell, at 795-430-7176. Correction! In-person event so no registration is required. Thursday, November 4, 2021, at 2:30-4:45 PM (EDT) | MSEE Atrium LECTURE | 2:30-3:30 PM (EDT) | Title: The Coming “Not So Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry 2:00-2:20 PM (EDT) | Speaker and participants are encouraged to arrive in advance to prepare and test equipment. 2:30-2:35 PM (EDT) | Welcome, PEDLS Overview and Introduction of Dean Mung Chiang: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering Introduction of Ravi Mahajan: × Mung Chiang, Executive Vice President of Purdue University for strategic initiatives, John A. Edwardson Dean of the College of Engineering, Roscoe H. George Distinguished Professor of Electrical and Computer Engineering 2:35-3:15 PM (EDT) | “The Coming “Not-So-Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry” – Lecture presented by: Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation 3:15-3:30 PM (EDT) | Q&A and Conclusion: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering INTERMISSION | 3:30-3:45 PM (EDT) | Participants are encouraged to arrive in advance to prepare and test equipment. PANEL| 3:45-4:45 PM (EDT)| Title: The Future of MicroChips Design 3:45-3:50 PM (EDT) | Welcome and Introduction of Carol Handwerker (Moderator) by: × Dimitrios Peroulis, Michael and Katherine Birck Head of Electrical and Computer Engineering, Reilly Professor of Electrical and Computer Engineering Introduction of Panelists by Carol Handwerker (Panel Moderator): Moderator: * Carol Handwerker, Reinhardt Schuhmann Jr. Professor of Materials Engineering Panelists: * Zhihong Chen, Professor of Electrical and Computer Engineering * Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation * Anand Raghunathan, Professor of Electrical and Computer Engineering * Ganesh Subbarayan, Professor of Mechanical Engineering 3:50-4:30 PM PM (EDT) | “The Future of Microchips Design?” 4:30-4:45 PM (EDT) | Q&A and Conclusion: * Carol Handwerker, Reinhardt Schuhmann Jr. Professor of Materials Engineering Dean Mung Chiang’s Bio: Mung Chiang is the Executive Vice President of Purdue University for strategic initiatives, the John A. Edwardson Dean of the College of Engineering, and the Roscoe H. George Distinguished Professor of Electrical and Computer Engineering. Purdue Engineering in 2021 became the largest engineering school to ever ranked among top five in the U.S. During 2019-20, he served as the Science and Technology Adviser to the U.S. Secretary of State and the chief global technology office in the Department of State to launch Technology Diplomacy. Prior to 2017, he was the Arthur LeGrand Doty Professor of Electrical Engineering, the inaugural Chair of Princeton Entrepreneurship Council and Director of Keller Center for Engineering Education at Princeton University. His research on communication networks received the 2013 Alan T. Waterman Award, the highest honor to scientists and engineers under the age of 40 in the U.S. A recipient of a Guggenheim Fellowship and the IEEE Tomiyasu Technical Achievement Award, he was elected to the National Academy of Inventors and the Royal Swedish Academy of Engineering Sciences. He founded the Princeton EDGE Lab in 2009 and co-founded several startup companies and an industry consortium in mobile networks, IoT and AI. A recipient of the ASEE Terman Education Award, his textbooks and online courses have reached hundreds of thousands of students. PEDLS Overview & Introduction Statement: Beginning in 2018, the Purdue Engineering Distinguished Lecture Series invites world-renowned faculty and professionals to Purdue Engineering to encourage thought-provoking conversations and ideas with faculty and students regarding the grand challenges and opportunities in their fields. Besides presenting a lecture to a broad audience of faculty, graduate and undergraduate students, they engage in an interactive panel with Purdue faculty and students. * - Speaker: Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding; ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT; Assembly Technology, Intel Corporation Bio: Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award For Excellence and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. Link to bio.<https://eps.ieee.org/technology/9-about-cpmt/313-bio-mahajan.html> - Lecture Title: The Coming “Not So Quiet” Revolutions: How Advanced Packaging Will Shape the Semiconductor Industry Lecture Abstract: Advanced packaging technologies are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power efficient platforms. This talk will first review the evolution of packaging to set context and describe the increasing value of packaging as an HI platform. Different packaging architectures will be compared on the basis of their physical interconnect capabilities, power delivery, power removal, and high bandwidth signaling capabilities. Key features in leading edge 2D and 3D technologies, will be described and a roadmap for their evolution will be presented. Specific examples, showing how product implementations take advantage of these technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust advanced package architectures. In addition to performance characteristics, this talk will also illustrate key opportunities and challenges in materials development, manufacturability and reliability, and describe how well-defined industry-academia partnerships can continue to ensure successful evolution of the HI roadmap. Panel Title: The Future of Microchips Design Panel Abstract: Microelectronics system architecture design is at the cusp of a technological shift with pervasive application of intelligence, modular chiplet integration enabling hybrid multi-die architecture, with ensuing security concerns with untrusted chiplets including DoS, snooping and side channels. The corresponding package-level hardware trends include 2.5D system in package with silicon or organic interposers, thinned stacked dies, and photonic integration. Complementing these system architecture and packaging trends are beyond CMOS technologies and BEOL innovations including novel metal and dielectric materials, and integrating novel devices and technologies at the intermediate interconnect layers. This panel will explore the drivers behind the technological trends and the research priorities that must be addressed to enable the microchips of the future. Thank you, Maria • • • Maria Longoria-Littleton Assistant Director, Faculty Success Programs College of Engineering