Dear all, I would like to invite you to my preliminary examination: Date: Nov 16, 2015 Time: 10:00 A.M. Place: Wang 1001 Refreshment will be available too. Details are as follows: Title: Reliability Physics of Transistors and ICs at the Scaling Limit Abstract:The microelectronic industry is in transition. At the device level, short-channel issues have led to the adoption of surround gate transistors, and at the system level, ICs with a large number of cores, different operating voltages, and technologies are being mounted on the same board. The surround gate transistors, such as FINFET, ETSOI, SOI-FinFET, GAA-FET, may be expensive because the fabrication process is complicated. Also, the surround gate geometry increases thermal resistance and self-heating, with corresponding penalty in reliability and lifetime. Isolated studies of self-heating have been reported, but a comprehensive analysis that compares various technologies in a systematic manner is missing and will be the first focus of this thesis. The heterogeneous integration of ICs defines the second challenge to be discussed in this thesis. Traditionally, high and low-voltage ICs had been separated by optical or inductive couplers. The area and power penalties are too high for modern applications. Innovative solutions involving capacitive voltage dividers – that reuses the backend dielectric stack – have been proposed, but the reliability of these stacks, especially subject to high voltage spikes, is unknown. -- Sincerely yours, Purdue University <https://engineering.purdue.edu/%7Ealam/> Shin, SangHoon / Research Assistant & Ph.D. student 765-430-1766/ shin136@purdue.edu <mailto:shin136@purdue.edu> Purdue University Office: 765-494-5988 / Fax: 765-494-2706 465 Northwestern Ave. West Lafayette, Indiana 47907-2035 https://engineering.purdue.edu/~alam/ <https://engineering.purdue.edu/%7Ealam/>
