Dear all, I will be taking my prelim on Feb 17, 2009 (Tuesday) at 10:00AM in EE317. You are all cordially invited to attend. Thanks. Title: ------ Theory and Characterization of Random Defect Formation and Its Implication in Variability of Nanoscale Transistors Abstract: ------------ With miniaturization of MOS transistors following Moore's law, oxide electric field under normal operation has continuously increased with each technology. Increasing oxide electric field does improve drive current and therefore the initial, time-zero, performance, however such high oxide electric field also strains the chemical bonds at the oxide/substrate interface and degrades transistor parameters over time. In addition, the incorporation of high-κ materials (like silicon oxynitride and hafnium-based materials) within the gate stack makes these transistors susceptible to trapping within the bulk of the dielectric (e.g., electron trapping for NMOS and hole trapping for PMOS). Taken together, these two phenomena cause rapid and time-dependent shift in threshold voltage (along with change in mobility, sub-threshold slope, etc.) in MOS transistors. This instability of threshold voltage - often referred to as Bias Temperature Instability or BTI - has become one of the major sources of CMOS variability in recent years. In addition to this defect-related phenomena, threshold voltage in small-scale transistors can also vary due to statistical process-related fluctuations. This thesis is focused on developing the theoretical framework and characterization techniques of BTI in PMOS transistors - generally known as Negative Bias Temperature Instability (NBTI) - by analyzing its functional dependencies over time, supply voltage, temperature, materials within the dielectric, and channel strain. This comprehensive analysis would allow identification of different features in modern NBTI characteristics. We recognize both interface trap and hole trapping as contributing factors for NBTI in modern CMOS technology. In some transistors, NBTI is dominated by interface traps and the mechanics of NBTI is modeled within an analytically tractable Reaction-Diffusion framework and compared with characteristic experimental signatures. In other transistors, hole trapping dominate and generalized Shockley-Read-Hall framework is used to model the kinetics of hole trapping in oxide traps. Taken together, this comprehensive theoretical framework - supported by detailed experiments - lead to a truly exciting possibility of the design of a variation-resilient transistor technology for CMOS architecture, a possibility - if demonstrated and adopted - may reshape how CMOS circuits are designed for handling major sources of threshold voltage fluctuations. ------------------------ Ehtesham ECE, Purdue University http://web.ics.purdue.edu/~aeislam