Dear all, Dallas Morisette<https://engineering.purdue.edu/ECE/People/ptProfile?resource_id=77034&_ga=2.229797465.474766276.1583755620-1222462354.1553101516>, Research Assistant Professor of Electrical and Computer Engineering will present this week’s faculty seminar series, Thursday, 3/12 @ 12pm (lunch provided) in BRK 2001. The first half will be an overview of research and the remainder will be open for questions and high-level discussion of collaboration opportunities that can lead to future center of excellence and/or also brainstorm about a shared vision for Birck. FinFET inspired SiC power MOSFETs Abstract: Silicon carbide (SiC) emerged as a viable semiconductor material in the early 1990’s. The earliest wafers were small, but wafer size and material quality has improved steadily, and today 100 and 150 mm nearly-defect-free wafers are commercially available from several suppliers. SiC power diodes entered commercial production in 2001, and have accumulated over 150 billion hours in the field with a failure rate 10x lower than silicon diodes. SiC MOSFETs entered production in 2011, and MOSFET sales recently surpassed $60 million per year. In spite of their progress, SiC power devices are still far from their theoretical limits of performance. This is especially true of power MOSFETs designed for the application rich space below 1 kV. The on-resistance of these SiC MOSFETs is currently limited by two elements: channel resistance due to the low mobility of electrons in the inversion layer, and substrate resistance. To make significant progress it is necessary to address both elements. In this talk, I will describe some of the innovative solutions we are pursuing that address both of these limitations. We reduce channel resistance by applying a “tri-gate” (3G) concept to power devices for the first time. The tri-gate geometry is used in 22 nm silicon CMOS technology to suppress short-channel effects. In SiC we use the 3G geometry for an entirely different reason: to increase the current-carrying width of the MOSFET channel without increasing the surface area. Using modifications of existing fabrication technology, the 3G structure can reduce MOSFET channel resistance by as much as an order-of-magnitude, without assuming any increase in channel mobility or improvement in interface quality. We reduce substrate resistance by forming a “waffle substrate” structure as the last step in the fabrication process. The waffle structure provides needed mechanical support, while reducing the resistance by as much as 5x below that of a thinned substrate alone. Please find below the BNC Spring Faculty Seminar Series schedule. Date Faculty Topic 1/30/2020 Ali Shakouri BNC Annex 2/6/2020 Allen Garner BioElectrica and ElectroPhysics 2/13/2020 Guang Lin Computational and predictive science and statistical learning both on algorithms and applications 2/20/2020 Lia Stanciu Design and fabrication of biosensors and chemical sensors 2/27/2020 Sunil Bhave Micromachining YIG 3/5/2020 Shriram Ramanathan Brain-inspired computing 3/12/2020 Dallas Morisette FinFET inspired silicon carbide power MOSFETs 3/19/20 Spring Break 3/26/20 Lunch with Dr. Moira Gunn Host of NPR’s Tech Nation and BioTech Nation Discovery Park Lecturer and Shark Tank Competition Judge 4/2/2020 Sophie Lelièvre 3D3C Cell Culture 4/9/2020 Jianguo Mei Challenges and Opportunities in R2R Manufacturing and Commercialization of Thin Film Electrochromics 4/16/2020 NanoDays 4/23/2020 Chi Hwan Lee Sticker-like Electronics (Sticktronics) for Wearable Health Monitoring 4/30/2020 Chen-Lung Hung Ultracold quantum gas and quantum optics 5/7/2020 Finals Week Thank you! Jaime Turner Lead Administrative Assistant to the Director | Birck Nanotechnology Center BRK | 1205 W State Street | West Lafayette, IN 47907 o: 765-494-3509<mailto:765-494-3509> | m: 765-491-3064<tel:7654913064> | jjturner@purdue.edu<mailto:jjturner@purdue.edu> [83324AA6]<https://www.purdue.edu/>