NSAC/NCN Seminar Series 2012 Topic: Non-planar 3D III-V MOSFETs for high-speed low-power logic applications Abstract: In this talk, we review recent developments on non-planar 3D III-V MOSFETs for high-speed low-power logic applications. In the 2011 ITRS roadmap, III-V MOSFETs have been considered promising candidate for Si CMOS at beyond 14nm technology node, due to its high mobility and saturation velocity. Targeting the 14nm channel length, we demonstrated non-planar 3D III-V transistors, including InGaAs FinFETs, HFinFET, and gate-all-around nanowire MOSFETs by top-down approach, to address the increasing demand for electrostatic control. Fabrication and characterization of the 3D III-V MOSFETs are summarized in this talk. Speaker: Jiangjiang Gu, PhD candidate(Prof. Peter Ye Group) in ECE, Purdue University Date/time: Thursday, March 1, 2012 3:30 PM- 4:30 PM at Birck 1001 Refreshment will served.