Seminars /Workshops / Events/Announcement
Prof. Venky Narayanamurti’s Birck Distinguished Lecture on Dec. 13, 2021 is now available on nanoHUB. See below the link:
https://nanohub.org/resources/35749
Rethinking the Nature and Nurture of Discovery Research
Venky Narayanamurti
Harvard University
Abstract
Research, particularly on the ?discovery? end of the R&D spectrum, is complex and easily misunderstood. Scientific advance doesn?t always precede, it often follows, engineering advance. Answering questions isn?t always the goal, finding questions often is.
We don?t always seek to strengthen conventional wisdom, sometimes we seek to surprise it. What if we could rethink research so that its nurturing, through policy and management, harmonizes with its nature?
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Announcement
Mask Protocols in the Cleanroom
We have observed various masking practices in the cleanroom recently so as a reminder for those using our Birck cleanroom, please continue to follow our COVID mask protocols. Masking requirements are either to use an M3 N95 mask by itself
or use a standard mask under the cleanroom veil. If you have any questions please contact a staff member.
Thanks,
Ron
Birck Engineering
JOB POSTINGS:
R&D Senior Design Engineer at Alpha & Omega Semiconductor
Alpha & Omega Semiconductor is looking for a Senior Design Engineer who will work in a dynamic team environment at AOS headquarter located in Sunnyvale, CA. The main responsibility of this position is to work
with marketing/process integration/product engineering group to develop silicon power device technology.
Application link:
Senior Design Engineer - Sunnyvale, CA - Alpha & Omega Semiconductor Jobs (applicantpro.com)
R&D Senior Process Integration Engineer at Alpha & Omega Semiconductor
Alpha & Omega Semiconductor is looking for a
Senior Process Integration Engineer who will work in a
dynamic team environment at AOS Semiconductor's leading technology fabrication facility (Jireh Semiconductor) located in Hillsboro, Oregon. The focus of this position is to work with device/process module/product engineering group to develop silicon power device
process technology and improve existing technology yield. Primary responsibilities are to process flow implementation, electrical characterization (failure analysis), and wafer level testing yield monitoring.
Application link:
Entry Level MS or PHD Process Integration R&D Engineer - Hillsboro, OR - Jireh Semiconductor Jobs (applicantpro.com)
Opening in OxideMEMS lab
Sunil Bhave’s OxideMEMS Lab explores inter-domain coupling in Opto-mechanical, Spin-Acoustic and Atom-MEMS devices. PhD, Postdoctoral and Research Associate positions
are available in these areas:
· Superconducting qubit and cryo-CMOS circuits
· Resonators and switches
· MEMS-engine for LIDAR
· Piezo-on-nitride transducers for atom-mechanics
Expertise in many and most of Microfabrication, PiezoMEMS, Photonics, Quantum Mechanics, Microwave circuits, PCB design, ADS/HFSS, Comsol, Python and Labview is required.
Please send CV to bhave@purdue.edu if you are
interested link
Nanofabrication Engineer at Microsoft
Microsoft Azure Quantum at Station Q Purdue seeks a nanofabrication engineer in the device fabrication group. You will join a multi-disciplinary team of theoretical
and experimental physicists, materials scientists, and hardware and software engineers working at the forefront of quantum computing. You should have experience in device fabrication and characterization techniques. Our work at Station Q Purdue in West Lafayette,
Indiana is part of global Microsoft Quantum research effort in topological quantum computing.
Responsibilities:
Responsibilities include develop, operate, and characterize semiconductor device fabrication processes in the Birck Nanotechnology Center cleanroom facilities located
at Purdue University. Accurately documenting and effectively communicating all procedures and results to the larger research group is an essential aspect of the position. The candidate may also be required to assist in the maintenance of equipment.
Qualifications:
A successful candidate must have:
•
• Master’s degree in Physics, Materials Science or Electrical Engineering. Other engineering disciplines will also be considered.
•
• Hands-on experience working with some or all of the following semiconductor process areas: lithography, thin film deposition and etch.
•
• Ability to follow protocols to operate sophisticated experimental equipment and to safely work with industrial solvents, acids, and bases in a cleanroom environment
•
• Excellent written and oral communication skills.
•
• Proficiency at accurately documenting processes and protocols.
•
• Strong attention to detail and good organizational skills.
•
• Strong desire to work in a collaborative international team.
Preference may be given to candidates with the following additional qualifications:
•
• Industry experience in semiconductor device process integration.
•
• Expertise in thin film characterization, both structural and electrical.
•
• Familiarity with design and layout tools for chip scale devices.
Please send your resume to
flgriggi@microsoft.com, selected candidates will be contacted for interviews.
Graduate Research Assistantship Opportunity:
Deposited Gate Oxides for SiC MOSFETs
Up to two graduate research assistantships are available in the area of silicon carbide metal-oxide-semiconductor (MOS) devices. SiC is a wide bandgap semiconductor with a high critical field, making it an exciting material for power electronic
devices. SiC MOSFETs are now commercially available, but do not yet achieve their full potential. Our group is approaching this problem from several directions, including a new device trench MOSFET geometries inspired by modern FinFETs and alternative gate
insulator fabrication methods.
Research activities will include fabrication and characterization of SiC MOS capacitors and MOSFETs with gate oxides formed by thermal oxidation, atomic layer deposition (ALD), and other methods. The student will gain a detailed understanding
of the physics of the MOS interface and will learn various methods of characterizing devices, including MOS CV analysis, interface state density and carrier mobility.
For more information or to apply, send resume and contact information to:
Dallas Morisette
Research Assistant Professor
NSAC Fab Forum
NSAC Fab Forum every Tuesday 2:00pm-2.30pm
NSAC Coffee Hour
NSAC Fab Forum every Friday 2:00pm-2.30pm
Birck Nanotechnology Center Advanced Capabilities
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***To post an announcement in the weekly BNC E-news please send to
Sangeeta Abrol @ abrols@purdue.edu***
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