Happy Holidays

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Seminars /Workshops / Events/Announcement

Announcement

On behalf of the Birck Leadership Team…….

Dear Birck Research Community,

The Purdue winter recess occurs December 23^rd through January 2. The university is officially closed during this time and reopens on Monday January 3. As we have done in past years, the Birck Nanotechnology Center will remain available for research but will be unstaffed and hazardous gasses will be unavailable. As always if you plan to do any work over the recess please follow all applicable Protect Purdue protocols. Following is a description of the Birck center during this period of university closure:

All labs and cleanroom will be open.
All hazardous gases will be unavailable.
HF, BOE, and TMAH chemical processing will be allowed as long as a buddy is present.
Precursors for ALD systems will be available.
No shipping or receiving is being done at any building on campus.
The custodians will not be working so restrooms will not be maintained, and sanitation of touch surfaces will not be done.

We encourage users to keep the facility clean and be extra vigilant about the hygiene and COVID risks.

A few engineering and building staff may walk through occasionally for major issues but availability will be very limited and could be impacted due to COVID restrictions.

Faculty and senior researchers are encouraged to be more proactive (e.g. occasional walk throughs checking the labs where there is ongoing research). Email Birck management if you notice anything.

Since there will be limited staff support during this winter recess the research groups are strongly encouraged to accomplish as much processing as possible before gases are turned off on Dec. 22.

See the following for more detailed information (this will be up on the BNC Wiki):

2021-12-23 to 2022-01-03: Reduced Holiday Operations

Due to Purdue’s Winter Recess hazardous gases will be unavailable from 3:30 PM Wednesday, December 22 until 8:00 AM on Monday, Jan 3^rd. Lab work may otherwise proceed, though any fume hood work must be done with someone else present in the same laboratory or cleanroom bay (the “buddy” system). Please note the following changes to our normal operation:

ALD sources will remain available

Unavailable gases:

Ammonia (NH3)
Boron trichloride (BCl3)
Chlorine (Cl2)
Dichlorosilane (H2Cl2Si)
Hydrogen (H2)
Hydrogen Sulfide (H2S)
Krypton Fluoride (KrF)
Methane (CH4)
Nitric Oxide (NO)
Silane (SiH4)
Trichlorosilane (HCl3Si)

Tools affected:

Reduced capability:

PVD Nitride Sputtering System (NH3 unavailable)
Tube 1 Clean Ox (H2 unavailable, dry oxidation only)
Tube 4 Field OX (H2 unavailable, dry oxidation only)

Tube 7 General Oxidation (H2 unavailable, dry oxidation only)
Panasonic (Cl2 and BCl3 unavailable)
Plasma-Therm Apex SLR ICP RIE Etcher (H2, Cl2 and BCl3 unavailable)

Shutdown:

Axic PECVD (NH3 & SiH4 unavailable)
Easy Tube 3000 DVD (CH4 unavailable)
Epigress (SiH4 unavailable)
H2S CVD (H2S & H2 unavailable)
Nitric Oxide Anneal (NO unavailable)
Plasma-Therm Apex SLR HDPCVD (SiH4 unavailable)
Tube 2 Nitride (NH3 and HCl3Si unavailable)
Tube 3 LTO (SiH4 unavailable)
Tube 6 Polysilicon (SiH4 unavailable)

Work with highly dermally toxic materials (25% TMAH, BOE, HF) ABSOLUTELY requires a buddy within eyesight at all times.
Custodial staff will not be working.
There will be limited restocking of shared use supplies.
There will be limited availability of engineering staff to answer questions or repair down equipment.

On metallization tools sources will not be changed and depositions must be < 200 nm.

Contact Steve Jurss (sejurss@purdue.edu) with any questions.

Mask Protocols in the Cleanroom

We have observed various masking practices in the cleanroom recently so as a reminder for those using our Birck cleanroom, please continue to follow our COVID mask protocols. Masking requirements are either to use an M3 N95 mask by itself or use a standard mask under the cleanroom veil. If you have any questions please contact a staff member.

Thanks,

Ron

Birck Engineering

In accordance with Procurement and Accounts Payable’s year end deadlines, here are the associated EOBOC Procurement Center’s deadlines:

Procurement Type	EOBOC Deadline	Central Deadline
ZV60s (including personal payments)	Friday 12/3	Wed. 12/8
Ariba orders >$10K	Wed. 12/8	Friday 12/10
Ariba (<$10K) and/or CC orders - to be delivered by 12/17**	Friday 12/10

**No deliveries accepted Dec. 23-Jan. 2 for holidays and winter recess

Thank you,

Cindy Sanders

Lead Business Assistant

Purdue University

Birck Nanotechnology

1205 W. State Street

West Lafayette, IN 47907

Birck Events and Birck News

JOB POSTINGS:

R&D Senior Design Engineer at Alpha & Omega Semiconductor

Alpha & Omega Semiconductor is looking for a Senior Design Engineer who will work in a dynamic team environment at AOS headquarter located in Sunnyvale, CA. The main responsibility of this position is to work with marketing/process integration/product engineering group to develop silicon power device technology.

Application link: Senior Design Engineer - Sunnyvale, CA - Alpha & Omega Semiconductor Jobs (applicantpro.com)

R&D Senior Process Integration Engineer at Alpha & Omega Semiconductor

Alpha & Omega Semiconductor is looking for a Senior Process Integration Engineer who will work in a dynamic team environment at AOS Semiconductor's leading technology fabrication facility (Jireh Semiconductor) located in Hillsboro, Oregon. The focus of this position is to work with device/process module/product engineering group to develop silicon power device process technology and improve existing technology yield. Primary responsibilities are to process flow implementation, electrical characterization (failure analysis), and wafer level testing yield monitoring.

Application link: Entry Level MS or PHD Process Integration R&D Engineer - Hillsboro, OR - Jireh Semiconductor Jobs (applicantpro.com)

Opening in OxideMEMS lab

Sunil Bhave’s OxideMEMS Lab explores inter-domain coupling in Opto-mechanical, Spin-Acoustic and Atom-MEMS devices. PhD, Postdoctoral and Research Associate positions are available in these areas:

· Superconducting qubit and cryo-CMOS circuits
· Resonators and switches
· MEMS-engine for LIDAR
· Piezo-on-nitride transducers for atom-mechanics
Expertise in many and most of Microfabrication, PiezoMEMS, Photonics, Quantum Mechanics, Microwave circuits, PCB design, ADS/HFSS, Comsol, Python and Labview is required.
Please send CV to bhave@purdue.edu if you are interested link

Nanofabrication Engineer at Microsoft

Microsoft Azure Quantum at Station Q Purdue seeks a nanofabrication engineer in the device fabrication group. You will join a multi-disciplinary team of theoretical and experimental physicists, materials scientists, and hardware and software engineers working at the forefront of quantum computing. You should have experience in device fabrication and characterization techniques. Our work at Station Q Purdue in West Lafayette, Indiana is part of global Microsoft Quantum research effort in topological quantum computing.

Responsibilities:

Responsibilities include develop, operate, and characterize semiconductor device fabrication processes in the Birck Nanotechnology Center cleanroom facilities located at Purdue University. Accurately documenting and effectively communicating all procedures and results to the larger research group is an essential aspect of the position. The candidate may also be required to assist in the maintenance of equipment.

Qualifications:

A successful candidate must have:

• • Master’s degree in Physics, Materials Science or Electrical Engineering. Other engineering disciplines will also be considered.

• • Hands-on experience working with some or all of the following semiconductor process areas: lithography, thin film deposition and etch.

• • Ability to follow protocols to operate sophisticated experimental equipment and to safely work with industrial solvents, acids, and bases in a cleanroom environment

• • Excellent written and oral communication skills.

• • Proficiency at accurately documenting processes and protocols.

• • Strong attention to detail and good organizational skills.

• • Strong desire to work in a collaborative international team.

Preference may be given to candidates with the following additional qualifications:

• • Industry experience in semiconductor device process integration.

• • Expertise in thin film characterization, both structural and electrical.

• • Familiarity with design and layout tools for chip scale devices.

Please send your resume to flgriggi@microsoft.com, selected candidates will be contacted for interviews.

Graduate Research Assistantship Opportunity:

Deposited Gate Oxides for SiC MOSFETs

Up to two graduate research assistantships are available in the area of silicon carbide metal-oxide-semiconductor (MOS) devices. SiC is a wide bandgap semiconductor with a high critical field, making it an exciting material for power electronic devices. SiC MOSFETs are now commercially available, but do not yet achieve their full potential. Our group is approaching this problem from several directions, including a new device trench MOSFET geometries inspired by modern FinFETs and alternative gate insulator fabrication methods.

Research activities will include fabrication and characterization of SiC MOS capacitors and MOSFETs with gate oxides formed by thermal oxidation, atomic layer deposition (ALD), and other methods. The student will gain a detailed understanding of the physics of the MOS interface and will learn various methods of characterizing devices, including MOS CV analysis, interface state density and carrier mobility.

For more information or to apply, send resume and contact information to:

Dallas Morisette

Research Assistant Professor

morisett@purdue.edu