Dear all, I would like to invite you to my final examination: Date: Feb 27, 2017 Time: 02:30 P.M. Place: Birck 2001 Refreshment will be available too. Details are as follows: Title: Implications of Self-Heating on Performance and Reliability of Confined Geometry Transistors and Integrated Circuits Abstract: The microelectronic industry is in transition. At the device level, short-channel issues have led to the adoption of floating body transistors, and at the system level, ICs with a large number of cores, different operating voltages, and technologies are being mounted on the same board. The floating body transistors, such as FINFET, ETSOI, SOI-FinFET, GAA-FET, may be expensive because the fabrication process is complicated. Also, the floating body geometry increases thermal resistance and self-heating, with the corresponding penalty in reliability and lifetime. Isolated studies of self-heating have been reported, but a comprehensive analysis that compares various technologies in a systematic manner is missing and will be the first focus of this thesis. The heterogeneous integration of ICs defines the second challenge to be discussed in this thesis. Traditionally, high and low-voltage ICs had been separated by optical or inductive couplers. The area and power penalties are too high for modern applications. Innovative solutions involving capacitive voltage dividers – that reuses the backend dielectric stack – have been proposed, but the reliability of these stacks, especially subject to high voltage spikes, is unknown. Towards this goal, we use our broad collaboration with industry and academia to develop a comprehensive conceptual framework for these two end-of-the-roadmap reliability challenges. Specially, in this thesis we explore the emerging reliability challenges from a single transistor to ICs. We will (i) identify the performance and reliability issues with the floating body transistors, (ii) analyze the self-heating issues by the electrical and optical characterizations for mapping heat transfers in the transistor, (iii) develop new reliability models accounting for the self-heating, (iv) predict implications of the self-heating in Ge CMOS technologies by the digital circuit simulation, (v) provide solutions to suppress the self-heating in the floating body transistor, and (iv) take a look reliability concerns with intermetal level. Overall, our works provide the framework for the comprehensive understanding of the emerging reliability concerns with sub 10nm technology nodes. -- -- Sincerely yours, Purdue University <https://engineering.purdue.edu/%7Ealam/> Shin, SangHoon / Research Assistant & Ph.D. student 765-430-1766/ shin136@purdue.edu <mailto:shin136@purdue.edu> Purdue University Office: 765-494-5988 / Fax: 765-494-2706 465 Northwestern Ave. West Lafayette, Indiana 47907-2035 https://engineering.purdue.edu/~alam/ <https://engineering.purdue.edu/%7Ealam/> Application AgQaa7bT2SiKipmjPHIvMz is unavailable