[cid:image006.png@01D7401C.A3F567B0] Seminars /Workshops / Events/Announcement SMART Industry Consortium Special Seminar Flexible Hybrid Electronics - Process Development and Applications John Williams, Ph.D., Technical Fellow Boeing Research and Technology, Huntsville, AL 35824 (256) 937-5904, john.d.williams14@boeing.com<mailto:john.d.williams14@boeing.com> Zoom Meeting: https://purdue-edu.zoom.us/j/95587242053 (Note: this seminar won't be recorded) Time: Thursday Jan 20, 2022 09:00-10:30 AM EST Boeing is actively engaged in the development of Flexible Hybrid Electronics. We began with single layer processes and have expanded rapidly prototype development of multilayer flexible printed circuit boards (Flex-PCBs) for size weight power and cost saving applications. Flex PCBs allow electronics to be wrapped onto cylindrical or bi-axial curved surfaces. Conventional Flex PCBs contain either one to four copper layers with limited electronic packaging. Most devices are bonded to rigid boards that contain complex packaged electronics. Boeing's processes, however, apply copper clad or printed inks on polyimide substrates to build fully functional flex-PCBs up to eight conductive layers thick. Thus allowing antennas, sensors, communication links, and radars to be placed directly onto the surface of a vehicle. Similarly, power routing, and microcontrollers can conform to surfaces or interior cavities. This technology represents a transformative approach to packaging PCBs in aerospace applications. Our team has demonstrated this capability on RF boards with no less than 500 through vias, 100 buried vias, and 50 electronically packaged components. Complex boards can be turned in days without electroplating. Pyralux AP polyimide substrates from DuPont, Taconic, and 3M bonding adhesive achieves alignment errors of 2 mil or less over an 8 x 10 square inch area. Kapton substrates can also be used with additional alignment error. Patterning can be completed with either copper clad material or silver ink. Vias are filled using conductive inks. Electronic packaging is currently performed using anisotropic conductive epoxy, but industrially standard solder attach is also available for copper clad and plated devices. Cost models have been completed for printed silver devices, documenting the manufacturability from Manufacturing Readiness Levels (MRL) 4 to 6. We are currently examining pilot capability of different suppliers to manufacture devices at volumes needed for commercial activities. [clip_image001]John D. Williams received his PhD in Engineering Science from LSU in 2004 and became a NextFlex Fellow in 2019 and a Boeing Technical Fellow in 2022. John has 17 years of Principal Investigator experience in device fabrication and is currently the principal investigator on numerous NextFlex contracts focused on antenna arrays and multilayer printing on curved surfaces. John is currently developing Additive Electronics Technologies (AET) for use on Boeing platforms. From 2004 to 2014 he served as a Senior Member of the Technical Staff at Sandia National Laboratories, and as an Assistant Professor of Electrical, Optical and Material Engineering at the University of Alabama in Huntsville (UAH). He joined Boeing in 2014 to found the Boeing Research and Technology AET effort in Huntsville where his team performs novel research in microwave filters, antennas, and flexible hybrid electronic (FHE) sensors by maturing manufacturing capabilities, implementing modeling and simulation, and developing prototype demonstrators. John is the principal / co-principal investigator for 4 concurrent NextFlex MII Projects. He has led, or co-led, 7 other NextFlex projects, serves on the NextFlex Technical Council, and is an industry co-lead for the NextFlex Materials Technical Working Group. He also serves as an industrial committee member for the ManTech JDMTP Electronics Subpanel. In 2021 he served on the organizing committee for the IEEE International Flexible Electronics Technologies Conference (IFETC). John has published more than 30 peer reviewed articles, over 30 US patents, 17 international patents, 4 Boeing trade secrets, and dozens of pending patents. John's Boeing related inventions on microwave filters, conformal antennas, hyperspectral metrology, and cryogenic cooling of MW class EMI filters are currently being developed for multiple BR&T efforts. ************** Zoom Details: Ali Shakouri is inviting you to a scheduled Zoom meeting. Topic: Williams/Boeing (Virtual SMART Seminar Purdue) Time: Jan 20, 2022 09:00 AM America/Indiana/Indianapolis Join Zoom Meeting https://purdue-edu.zoom.us/j/95587242053 Meeting ID: 955 8724 2053 One tap mobile +13126266799,,95587242053# US (Chicago) +16465588656,,95587242053# US (New York) Dial by your location +1 312 626 6799 US (Chicago) +1 646 558 8656 US (New York) +1 301 715 8592 US (Washington DC) +1 346 248 7799 US (Houston) +1 669 900 6833 US (San Jose) +1 253 215 8782 US (Tacoma) Meeting ID: 955 8724 2053 Find your local number: https://purdue-edu.zoom.us/u/adb0xp6lCJ ************** Prof. Venky Narayanamurti's Birck Distinguished Lecture on Dec. 13, 2021 is now available on nanoHUB. See below the link: https://nanohub.org/resources/35749 Rethinking the Nature and Nurture of Discovery Research Venky Narayanamurti Harvard University Abstract Research, particularly on the ?discovery? end of the R&D spectrum, is complex and easily misunderstood. Scientific advance doesn?t always precede, it often follows, engineering advance. Answering questions isn?t always the goal, finding questions often is. We don?t always seek to strengthen conventional wisdom, sometimes we seek to surprise it. What if we could rethink research so that its nurturing, through policy and management, harmonizes with its nature? ************ Workshop Hi All Members of BNC, I will be running CasaXPS workshop to teach how to analyze XPS data from January 18-20,2022 at 9.00am-1.00pm. Registration at: https://forms.gle/GJPLr58Yqugry5Mk6 Best regards, Dmitry ***************************************** Dmitry Zemlyanov, PhD Senior Research Scientist - Surface Science Application Purdue University Birck Nanotechnology Center, 1205 West State Street, West Lafayette, IN 47907-2057 Tel.: +1 (765) 496-2457 (office - BRK 1274) +1 (765) 496-6217 (lab - BRK 1077) Cell: +1 (765) 427-3813 Fax: +1 (765) 496-8299 mailto:dzemlian@purdue.edu web: https://www.purdue.edu/discoverypark/birck/facilities/equipment/Characteriza... Announcement Mask Protocols in the Cleanroom We have observed various masking practices in the cleanroom recently so as a reminder for those using our Birck cleanroom, please continue to follow our COVID mask protocols. Masking requirements are either to use an M3 N95 mask by itself or use a standard mask under the cleanroom veil. If you have any questions please contact a staff member. Thanks, Ron Birck Engineering Birck Events<https://www.purdue.edu/discoverypark/birck/events/index.php> and Birck News<https://www.purdue.edu/discoverypark/birck/news/index.php> JOB POSTINGS: R&D Senior Design Engineer at Alpha & Omega Semiconductor Alpha & Omega Semiconductor is looking for a Senior Design Engineer who will work in a dynamic team environment at AOS headquarter located in Sunnyvale, CA. The main responsibility of this position is to work with marketing/process integration/product engineering group to develop silicon power device technology. Application link: Senior Design Engineer - Sunnyvale, CA - Alpha & Omega Semiconductor Jobs (applicantpro.com)<https://caosmd.applicantpro.com/jobs/2050960.html> R&D Senior Process Integration Engineer at Alpha & Omega Semiconductor Alpha & Omega Semiconductor is looking for a Senior Process Integration Engineer who will work in a dynamic team environment at AOS Semiconductor's leading technology fabrication facility (Jireh Semiconductor) located in Hillsboro, Oregon. The focus of this position is to work with device/process module/product engineering group to develop silicon power device process technology and improve existing technology yield. Primary responsibilities are to process flow implementation, electrical characterization (failure analysis), and wafer level testing yield monitoring. Application link: Entry Level MS or PHD Process Integration R&D Engineer - Hillsboro, OR - Jireh Semiconductor Jobs (applicantpro.com)<https://aosmd.applicantpro.com/jobs/1949301.html> Opening in OxideMEMS lab Sunil Bhave's OxideMEMS Lab <https://engineering.purdue.edu/oxidemems/publications.html> explores inter-domain coupling in Opto-mechanical, Spin-Acoustic and Atom-MEMS devices. PhD, Postdoctoral and Research Associate positions are available in these areas: * Superconducting qubit and cryo-CMOS circuits * Resonators and switches * MEMS-engine for LIDAR * Piezo-on-nitride transducers for atom-mechanics Expertise in many and most of Microfabrication, PiezoMEMS, Photonics, Quantum Mechanics, Microwave circuits, PCB design, ADS/HFSS, Comsol, Python and Labview is required. Please send CV to bhave@purdue.edu<mailto:bhave@purdue.edu> if you are interested link<http://interested.link> Nanofabrication Contractor Engineer for Microsoft Quantum Microsoft Azure Quantum at Station Q Purdue seeks a nanofabrication engineer in the device fabrication group. You will join a multi-disciplinary team of theoretical and experimental physicists, materials scientists, and hardware and software engineers working at the forefront of quantum computing. You should have experience in device fabrication and characterization techniques. Our work at Station Q Purdue in West Lafayette, Indiana is part of global Microsoft Quantum research effort in topological quantum computing. Responsibilities: Responsibilities include develop, operate, and characterize semiconductor device fabrication processes in the Birck Nanotechnology Center cleanroom facilities located at Purdue University. Accurately documenting and effectively communicating all procedures and results to the larger research group is an essential aspect of the position. The candidate may also be required to assist in the maintenance of equipment. Qualifications: A successful candidate must have: * * Master's degree in Physics, Materials Science or Electrical Engineering. Other engineering disciplines will also be considered. * * Hands-on experience working with some or all of the following semiconductor process areas: lithography, thin film deposition and etch. * * Ability to follow protocols to operate sophisticated experimental equipment and to safely work with industrial solvents, acids, and bases in a cleanroom environment * * Excellent written and oral communication skills. * * Proficiency at accurately documenting processes and protocols. * * Strong attention to detail and good organizational skills. * * Strong desire to work in a collaborative international team. Preference may be given to candidates with the following additional qualifications: * * Industry experience in semiconductor device process integration. * * Expertise in thin film characterization, both structural and electrical. * * Familiarity with design and layout tools for chip scale devices. Please send your resume to flgriggi@microsoft.com<mailto:flgriggi@microsoft.com>, selected candidates will be contacted for interviews. Graduate Research Assistantship Opportunity: Deposited Gate Oxides for SiC MOSFETs Up to two graduate research assistantships are available in the area of silicon carbide metal-oxide-semiconductor (MOS) devices. SiC is a wide bandgap semiconductor with a high critical field, making it an exciting material for power electronic devices. SiC MOSFETs are now commercially available, but do not yet achieve their full potential. Our group is approaching this problem from several directions, including a new device trench MOSFET geometries inspired by modern FinFETs and alternative gate insulator fabrication methods. Research activities will include fabrication and characterization of SiC MOS capacitors and MOSFETs with gate oxides formed by thermal oxidation, atomic layer deposition (ALD), and other methods. The student will gain a detailed understanding of the physics of the MOS interface and will learn various methods of characterizing devices, including MOS CV analysis, interface state density and carrier mobility. For more information or to apply, send resume and contact information to: Dallas Morisette Research Assistant Professor morisett@purdue.edu<mailto:morisett@purdue.edu> NSAC Fab Forum NSAC Fab Forum every Tuesday 2:00pm-2.30pm NSAC Coffee Hour NSAC Fab Forum every Friday 2:00pm-2.30pm Birck Nanotechnology Center Advanced Capabilities AJA Ion Mill [cid:image013.png@01D80C3D.1C67E960]<https://wiki.itap.purdue.edu/display/BNCWiki/AJA+ICP+Argon+Ion+Mill+Etcher> * Direct physical milling of thin and thick films using argon atoms. * Water-cooled rotating sample carrier can be oriented 0-90 degrees from normal beam incidence. * Secondary ion mass spectrometer (SIMS) mounted on the system can be used for manual or automatic endpoint detection (EPD) Other Capabilities: * Ion beam source : inductively-coupled argon plasma, accelerated up to 900 V in a 14cm broad beam with currents up to 620 mA (Kaufman & Robinson, Inc.). * Ar+ ions neutralized using a matched electron beam current before reaching the sample. * Sample load-lock system saves time with processing Location: BRK Cleanroom Bay Q Contact: Neil Dilley (ndilley@purdue.edu) <mailto:ndilley@purdue.edu> Please visit the Birck Wiki to learn about the wide array of fabrication and characterization equipment at the facility<https://wiki.itap.purdue.edu/display/BNCWiki/> ***To post an announcement in the weekly BNC E-news please send to Sangeeta Abrol @ abrols@purdue.edu***<mailto:abrols@purdue.edu***> Follow us on Facebook and Twitter [Facebook icon]<https://www.facebook.com/nano.purdue.edu/> [Twitter icon] <https://twitter.com/BNCPurdue>
