October 2016 - BNC-all - ecn.purdue.edu

Jaijeet Roychowdhury, UC Berkeley Seminars Thursday, Nov. 3rd.
by Anthrop, Heather L 31 Oct '16

31 Oct '16

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E-news for the week of October 31st
by Anthrop, Heather L 31 Oct '16

31 Oct '16

Seminar Ying Diao Thursday, December 1st at 1:30 pm Birck Nanotechnology Center room 1001 For more information please visit: https://nanohub.org/groups/bnc/calendar/details/1509 Reminder of Fume Hood Work Requirements Since Ira's retirement, there have been a number of cases of users not adhering to facility safety and cleanliness rules, particularly in the lithography hoods. As a reminder: * Chemical safety goggles are required any time you're within the yellow striped line around fume hoods * Your head should never be in a fume hood when anyone is doing wet chemistry * All solvent/developer bottles need to be returned to their proper storage location when you're finished with them, even if you didn't find them in their proper location Additional Vented Waste Can Installed As a follow-up to an input from a few weeks ago, where a user commented that the waste cans near the photolithography bay were producing unpleasant fumes, we procured a vented waste can and installed it in that area. Now there are two covered cans with exhausted vents in that bay, so please use these cans for any waste that includes photoresist and/or solvent materials so fumes may be exhausted away through the cleanroom exhaust system. Note there are still two cans in that location with no exhaust so please be sure to use those cans only for dry, non-volatile waste. Hot-Plate Exhaust Snorkels You may have noticed new snorkel-like exhaust lines installed individually over the hot plates in the aligner bay. These are connected to our house exhaust to evacuate evolved fumes from wafers being baked on the hot plates and this should alleviate the solvent scents that have occasionally been noticed in the area. Special thanks to Mike Fenters, our sheet metal tradesman who designed, fabricated, and installed the exhausted snorkels.

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CasaXPS Workshop Nov. 1-2, 2016
by Turner, Jaime J 28 Oct '16

28 Oct '16

[cid:image001.png@01D23133.61ABD530] Jaime Turner Administrative Assistant to the Director Birck Nanotechnology Center 1205 West State Street West Lafayette, IN 47907-2057 Email: jjturner(a)purdue.edu<mailto:jjturner@purdue.edu> Phone: 765-494-3509

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Fwd: NSAC Coffee Hour Announcement
by Sajid Choudhury 28 Oct '16

28 Oct '16

Just a reminder that we are having the NSAC Coffee hour now at the atrium ---------- Forwarded message ---------- From: Anthrop, Heather L <hanthrop(a)purdue.edu> Date: Thu, Oct 27, 2016 at 11:28 AM Subject: [BNC-all] NSAC Coffee Hour Announcement To: "bnc-all(a)ecn.purdue.edu" <bnc-all(a)ecn.purdue.edu> *NSAC Coffee Hour* Speaker: Evan Witkoske Title of the Talk: Nanoscale Lateral HBTs: (A Low Voltage Logic Switch?) Venue: BNC Attrium Date: 10/28/2016 Time: 3:30pm Abstract: Integrated circuit technology faces two important challenges: 1) continuing to downscale device dimensions and 2) reducing power. Given the enormous investment that has been made in the IC design infrastructure for CMOS, it would be highly desirable to develop a “drop-in replacement” for Si CMOS – one that could operate at lower voltages than Si CMOS, have better scaling properties, and that could be used in CMOS style circuits operating at the same or higher speeds. The HBT, with its absence of a thin gate dielectric, eliminates oxide scaling and electrostatic design challenges, while also allowing high turn on currents. To utilize HBTs for low-power CMOS, a small bandgap base and large bandgap emitter/collector with appropriate band offsets must be used. Parasitics must be minimized, but the major obstacle is recombination, which lead to high base currents. We show that if certain conditions are met, a low voltage, HBT with high drive currents is achievable and could serve as a drop in replacement for CMOS. _______________________________________________ BNC-all mailing list BNC-all(a)ecn.purdue.edu https://engineering.purdue.edu/ECN/mailman/listinfo/bnc-all

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John Weaver's retirement
by Peroulis, Dimitrios 27 Oct '16

27 Oct '16

Dear all, After a 45-year career, beginning with semiconductor manufacturing and evolving to nanotechnology facilities, John Weaver has elected to retire. He will be spending his retirement with his second passion, 19th Century coastal fortifications. John will be retiring effective February 17, 2017 - one day after his 67th birthday. John was instrumental in the implementation of the Birck Nanotechnology Center, leading the design, construction, startup, and operation of the facility. Please join me in thanking John for his critical contributions to our community and beyond and in wishing him the best in his retirement. We will honor John for his contributions in a farewell retirement party in February - details will be sent later. Best Dimitri ________________________________________________________________________________ Dimitrios Peroulis Professor, School of Electrical and Computer Engineering Deputy Director, Birck Nanotechnology Center Purdue University 1205 West State Street West Lafayette, IN 47907-2057 tel: (765) 494-3491 email: dperouli(a)purdue.edu<mailto:dperouli@purdue.edu> http://sites.google.com/site/peroulisteam/ ________________________________________________________________________________

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NSAC Coffee Hour Announcement
by Anthrop, Heather L 27 Oct '16

27 Oct '16

NSAC Coffee Hour Speaker: Evan Witkoske Title of the Talk: Nanoscale Lateral HBTs: (A Low Voltage Logic Switch?) Venue: BNC Attrium Date: 10/28/2016 Time: 3:30pm Abstract: Integrated circuit technology faces two important challenges: 1) continuing to downscale device dimensions and 2) reducing power. Given the enormous investment that has been made in the IC design infrastructure for CMOS, it would be highly desirable to develop a “drop-in replacement” for Si CMOS – one that could operate at lower voltages than Si CMOS, have better scaling properties, and that could be used in CMOS style circuits operating at the same or higher speeds. The HBT, with its absence of a thin gate dielectric, eliminates oxide scaling and electrostatic design challenges, while also allowing high turn on currents. To utilize HBTs for low-power CMOS, a small bandgap base and large bandgap emitter/collector with appropriate band offsets must be used. Parasitics must be minimized, but the major obstacle is recombination, which lead to high base currents. We show that if certain conditions are met, a low voltage, HBT with high drive currents is achievable and could serve as a drop in replacement for CMOS.

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FW: [Physfaculty] Notice: Condensed Matter Seminar, Friday, October 28, 2016 3:30 PM PHYS Room 203
by Black, Nancy Lee 26 Oct '16

26 Oct '16

Department of Physics and Astronomy Condensed Matter Seminar Friday October 28, 2016 3:30 PM Physics Rm 203 (Refreshments 3PM in Physics Rm 242) Professor Leo Kouwenhoven >From TU Delft University of Technology the Netherlands Experimental progress on Majoranas in semiconductors From: Manfra, Michael James Sent: Wednesday, October 26, 2016 1:27 PM To: Black, Nancy Lee <blackn(a)purdue.edu> Subject: FW: [Physfaculty] Notice: Condensed Matter Seminar, Friday, October 28, 2016 3:30 PM PHYS Room 203

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Congratulations!
by Anthrop, Heather L 25 Oct '16

25 Oct '16

[Image result for it's a girl] Congratulations to Rosa and her family! Baby Isabela was born on Wednesday, October 19th. Both mom and baby are doing well and are at home.

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BNC E-news for the week of Oct. 24th
by Anthrop, Heather L 24 Oct '16

24 Oct '16

I has been brought to our attention that students have been using chemicals that belong to either other individuals or groups. Please get permission from the individual or group before using any chemical that has either an individual or groups name on it. This could be considered theft. Thank you for your assistance, Stephen Safety Officer Birck Nanotechnology Center Thin Nitride Deposition Issues A user reported difficulty in using our 'silicon nitride evaporator' but we're not sure which system is being referenced. We have nitride sputtering, CVD nitride, and PECVD nitride but these are not evaporators. We would like to help with these types of issues but we need more details on which system is causing delays in research. If the person submitting this would like to discuss it please contact Ron or send an email to birckengineering(a)purdue.edu<mailto:birckengineering@purdue.edu>. Thanks much. Flow Injection Analysis Suggestion A user suggested a good addition to the BioCR would be a Flow Injection Analysis System. We appreciate these inputs and will put this on our equipment plan and roadmap. Dear Fellow Scientists, The 3D Cell Culture Core (3D3C) facility is proposing a first hands-on training workshop for visualization of 3D cell cultures on November 17 and 18, 2016. The workshop will cover some basic techniques for immunolabeling and dye staining and microscope observation of live and fixed 3D cell cultures. For details on the content, please see below and the flyer attached. The prerequisite for the workshop is REM biosafety training and blood-borne-pathogen training; sufficient knowledge in basic cell culture techniques is recommended. If you are interested in the workshop, please contact me for information and registration. The workshop is limited to SIX participants. The deadline for registration is October 28, 2016. Sincerely, Tim Kwok Facility Manager 3D Cell Culture Core (3D3C) Facility Birck Nanotechnology Center Purdue University [https://gallery.mailchimp.com/b7d6d1ffee56a866e499104cf/images/9c8a64b5-ab4…]

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Today's coffee hour
by Aveek Dutta 21 Oct '16

21 Oct '16

Dear all, Today's coffee hour will be from 3:30-4:00pm in the Birck Atrium. Today's presenter is Xingshu Sun. The title: "Channel Transmission Characteristics of Silicon Nanotransistors" Abstract: The drain and gate voltage dependent channel transmission, T(Vgs, Vds), plays a key role in determining the IV characteristics of nanoscale field-effect transistors. In this paper, we report measurements of T(Vgs, Vds) for n-channel Extremely Thin Silicon-On-Insulator (ETSOI) MOSFETs with channel lengths from 30 to 980 nm. The results confirm previously given estimates of for low and high drain bias. In addition, they also provide a complete description over the range of biases of interest. The results also show that for a given technology, the shape of T(Vgs, Vds) is independent of the channel length. Hope to see you all there. Best, Aveek Dutta Graduate Research Assistant Birck Nanotechnology Center Department of Electrical and Computer Engineering Purdue University

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